"<pre>
module P2100A

title 'P2100A'

"Version 4: [11-JAN-08] Slowed down SCK so we can 
"operate TLC1865 as well as the faster AD-series 
"ADCs. Remove 1 MHz sample rate. We simplify the
"logic by adjusting the number of sample thresholds
"and adding some dedicated nodes. We start the sss
"machine with an instruction. Compile time is now
"5 s and we use 136 out of 256 logic outputs.

"Version 3: [10-JAN-08 We add the SRC, NSC, RST,
"and SSS instructions. We implement a sample timer,
"data address, sample session state machine, and"
"ADC state machine.

"Version 2: [09-JAN-08] We add connections for the
"analog multiplexer and ADCs. We remove the message
"receiver code of P3007C04, which we don't need. Add
"Instruction Processor and Analog Multiplexer."

"Version 1: [27-DEC-07] This is the P3007C04 code, modified 
"to account for the new pin assignments in the A2100, but
"not including the new outputs that drive the CMOS switches. 
"We set the A3007C's comparator input (C) to zero, so the 
"firmware will receive no messages, and store only timestamps.
"We set the message clock equal to the data clock, and use an 
"80-MHz clock input to generate the data clock and synchronise 
"the reference clock.

declarations
  firmware_version=3;
  fake_data=1;
equations

"Pins"
declarations
A pin 3; "LVDS input"
B pin 10 istype 'com'; "LVDS output"
C=0; "Comparator Output"
LB pin 8 istype 'com'; "Loop Back"
!RESET pin 22;"Hardware Reset"			
ARCK pin 38; "Asynchronous 32.768 kHz reference clock input"
FCK pin 39; "Fast Clock 80 MHz."
!RW pin 59 istype 'com'; "RAM Write"
!RCE pin 66 istype 'reg'; "RAM Chip Enable"
!ROE pin 6 istype 'com'; "RAM Output Enable"
RA18..RA0 pin 85,80,79,78,16,17,19,31,30,53,
  54,55,56,58,67,69,70,71,72 istype 'reg'; "RAM Address"
RD7..RD0 pin 9,11,14,15,60,61,64,65 istype 'com'; "RAM Data"
ram_data = [RD7..RD0];
RECEIVE pin 97 istype 'reg'; "Receive Indicator, through monostable"
UPLOAD pin 94 istype 'com'; "Upload Indicator, through monostable"
EMPTY pin 98 istype 'com'; "Empty Indicator, direct to LED"
TP1 pin 47 istype 'com'; "Test Point 1"
TP2 pin 48 istype 'com'; "Test Point 2"
SS1 pin 41 istype 'com'; "Serial Select ADC 1"
SCK1 pin 42 istype 'com'; "Serial Clock ADC 1"
SDI1 pin 43 istype 'com'; "Serial Data In ADC 1"
SDO1 pin 44; "Serial Data Out ADC 1"
SS2 pin 35 istype 'com'; "Serial Select ADC 2"
SCK2 pin 34 istype 'com'; "Serial Clock ADC 2"
SDI2 pin 36 istype 'com'; "Serial Data In ADC 2"
SDO2 pin 28; "Serial Data Out ADC 2"
SVR1 pin 84 istype 'reg'; "Select ADC 1 Voltage Reference"
SVA1 pin 50 istype 'reg'; "Select ADC 1 Voltage Analog"
SVL1 pin 49 istype 'reg'; "Select ADC 1 Voltage Logic"
SVR2 pin 86 istype 'reg'; "Select ADC 2 Voltage Reference"
SVA2 pin 87 istype 'reg'; "Select ADC 2 Voltage Analog"
SVL2 pin 93 istype 'reg'; "Select ADC 2 Voltage Logic"
ON pin 29 istype 'reg'; "WAKE, turns on fixed voltages"
SVB pin 92 istype 'com'; "Select Voltage Bottom Reference"
SVT pin 81 istype 'reg'; "Select Voltage Top Reference"
equations


"Data Clock Generation"
"---------------------"

declarations
DCK node istype 'reg'; "Data Clock"
equations

"We divide the 80 MHz clock by two to create"
"the data clock."
DCK.clk=FCK;
DCK:=!DCK;

"Reference Clock"
"---------------"

declarations
RCK node istype 'reg'; "Reference Clock"
equations

"We synchronise the incoming 32.768 kHz clock"
"to DCK to create RCK."
RCK.clk=DCK;
RCK:=ARCK;


"LWDAQ Command and Address Decoding"
"----------------------------------"

"This LWDAQ receiver uses the 40-MHz data clock to generate"
"the DA and DDA signals. We synchronise the incoming serial"
"logic signal, A, with the data clock."

declarations
SA node istype 'reg'; "Synchronized A"
DSA node istype 'reg'; "Delayed SA"
DA node istype 'com,keep'; "Delayed A Rising Edge"
DDA node istype 'com,keep'; "Delayed DA"
AA node istype 'reg'; "Address Active"
DAA node istype 'reg'; "Delayed AA"
CA node istype 'reg'; "Command Active"
DCA node istype 'reg'; "Delayed CA"
ER,Q1..Q16 node istype 'reg'; "Receiver Bits"
LT3..LT0 node istype 'reg'; "LWDAQ Timer"
lt = [LT3..LT0];
AS node istype 'reg'; "Address Strobe"
CS node istype 'reg'; "Command Strobe"
DS node istype 'reg'; "Data Strobe"
DC1..DC16 node istype 'reg';"Device Command Bits"
DA0..DA15 node istype 'reg';"Device Address Bits"
WAKE node istype 'com'; "WAKE"
DTX node istype 'com'; "Device Transmit"
equations

"We synchronize A with DCK, and provide a delayed"
"version of A that allows us to detect edges."
[SA,DSA].clk = DCK;
[SA,DSA].aclr = RESET;
SA := A;
DSA := SA;

"This timer allows us to generate the Delayed A (DA)"
"and Double-Delayed A (DDA) signals for serial reception."
lt.clk = DCK;
lt.aclr = RESET;
when lt==^d0 then {
  when SA & !DSA then lt:=1
  else lt:=0;
} else {
  when lt==9 then lt:=0
  else lt:=lt+1;
}
DA = (lt==4);
DDA = (lt==9);

"We use DCK to clock the receiver registers, and RESET to"
"clear them."
[ER,Q1..Q16,AA,DAA,AS,CA,DCA,CS,DS,DC1..DC16,DA0..DA15].clk = DCK;
[ER,Q1..Q16,AA,DAA,AS,CA,DCA,CS,DS,DC1..DC16,DA0..DA15].aclr = RESET;

"We move bits along the shift register on DA."
when DA then [ER,Q1..Q16] := [SA,ER,Q1..Q15];
else [ER,Q1..Q16] := [ER,Q1..Q16];

"Address Active provides a pulse that begins with DDA"
"on the start bit of an address transmission, and ends"
"with the stop bit of an address transmission. Delayed"
"AA allows us to create Address Strobe, or AS. Address"
"Strobe provides a pulse at the end of an address"
"reception. We clock the receiver bits into the address"
"register on a rusing edge of AS."
when DDA then AA := (!AA & !CA & !SA & !ER) # (AA & !SA)
else AA := AA;
DAA := AA;
AS := DAA & !AA;
when AS then [DA0..DA15] := [Q1..Q16]
else [DA0..DA15] := [DA0..DA15];

"Command Active provides a pulse that begins with DDA"
"on the start bit of a command transmission, and ends"
"with the stop bit of a command transmission. Delayed"
"CA allows us to create Command Strobe, or CS. Command"
"strobe provides a pulse at the end of each command"
"reception. We clock the receiver bits into the command"
"register on a rising edge of CS."
when DDA then CA := (!AA & !CA & !SA & ER) # (CA & !SA)
else CA := CA;
DCA := CA;
CS := DCA & !CA;
when CS then [DC1..DC16] := [Q1..Q16]
else [DC1..DC16] := [DC1..DC16];

"Data Strobe identifies a solitary stop bit on A. A"
"solitary stop bit, combined with DTX, indicates that"
"the driver is expecting a byte transfer."
DS := DDA & SA & !AA & !CA;

"Device Transmit Bit"
DTX = DC5;

"We loop back A to B so long as DTX is not set."
when !DTX then B = A;

"We enable the return LVDS driver when DC7 is set."
LB = DC7;

"WAKE bit."
WAKE = DC8;


"Instruction Processor"
"---------------------"

"The instruction bits are Q16 down to Q9. We don't use"
"the latched bits DC16 down to DC9 for the same reason"
"we don't use DC6 in IS (see below)."
declarations
IS node istype 'com,keep'; "Instruction Strobe"
instruction = [Q16..Q9];
operation = [Q16..Q13];
argument = [Q12..Q9];
NOP = 0;
SSS = 1;
SFV = 2;
CMC = 3;
SRC = 4;
NSC = 5;
RST = ^hF;
IRST node istype 'com,keep'; "Instruction Reset"
equations

"When we receive a command with DC6 (called DRX in data"
"devices like this) set to 1, we execute DC16..DC9 (called"
"I7..I0 in the A2100) as an instruction. The IS (instruction"
"strobe) signal provokes execution. We use Q6 instead of DC6"
"in the strobe equation because Q6 is valid on the rising edge"
"of CS, but DC6 is clocked some time during the assertion of"
"CS."
IS = CS & Q6;

"The instruction reset is provoked by the instruction"
"command or by the hardware reset."
IRST = (IS & (operation == RST)) # RESET;


"Fixed Voltages"
"--------------"

ON.ap = IRST;
ON.clk = DCK;
when IS & (operation == SFV) then ON := (argument > 0);
else ON := ON;


"Analog Multiplexer"
"------------------"

"Here we interpret the current measurement channel number, as"
"set by the CMC operation, and select one of the eight current"
"measurement channels. We select SVB by default because it is"
"stable and small. Its analog return is not large enough to interfere"
"with the digital return."
[SVR1,SVA1,SVL1,SVR2,SVA2,SVL2,SVT].aclr = IRST;
[SVR1,SVA1,SVL1,SVR2,SVA2,SVL2,SVT].clk = DCK;
when IS & (operation == CMC) then {
  SVT  := (argument == ^h1);
  SVR1 := (argument == 2);
  SVA1 := (argument == 3);
  SVL1 := (argument == 4);
  SVR2 := (argument == 5);
  SVA2 := (argument == 6);
  SVL2 := (argument == 7);
} else {
  [SVR1,SVA1,SVL1,SVR2,SVA2,SVL2,SVT] 
    :=[SVR1,SVA1,SVL1,SVR2,SVA2,SVL2,SVT]
}
SVB = !SVT & !SVR1 & !SVA1 & !SVL1 & !SVR2 & !SVA2 & !SVL2;


"Number of Samples Code"
"----------------------"

declarations
NSC0..NSC3 node istype 'reg'; "Number of Samples Code"
nsc=[NSC3..NSC0];
equations

nsc.aclr = IRST;
nsc.clk = DCK;
when IS & (operation == NSC) then {
  nsc := argument;
} else {
  nsc := nsc;
}

"Sample Rate Code"
"----------------"

declarations
SRC0..SRC3 node istype 'reg'; "Sample Rate Code"
src=[SRC3..SRC0];
equations

src.aclr = IRST;
src.clk = DCK;
when IS & (operation == SRC) then {
  src := argument;
} else {
  src := src;
}


"Data Address"
"------------"

declarations
DAI node istype 'reg'; "Data Address Increment"
DAR node istype 'reg'; "Data Address Reset"
data_addr = [RA18..RA0]; "Data Address"
num_samples = [RA18..RA3]; "Number of Samples"
equations

"The data address is the RAM address at which we store"
"sample bytes and read sample bytes."
data_addr.clk = DCK;
data_addr.aclr = DAR;
when DAI then data_addr := data_addr+1;
else data_addr:=data_addr;


"Data Transmitter"
"----------------"

"The transmitter sends bytes back to the driver. It waits for"
"DS combined with DTX (DC5). When it receives DS and DTX, it"
"waits for Transmission Byte Load (TBL). The transmitter uses"
"DCK to time its serial transmission to the driver. It transmits"
"a leading zero followed by the eight bits of the transmission"
"byte (tb)."

declarations
TS4..TS0 node istype 'reg'; "Transmit State"
TB7..TB0 node istype 'reg'; "Transmission Bits"
ts=[TS4..TS0];"Transmission State"
tb=[TB7..TB0]; "Transmission Byte"
TBL node istype 'reg'; "Transmitter Byte Load"
TBO node istype 'com,keep'; "Transmitter Bit Out"
FDC0..FDC2 node istype 'reg'; "Fake Data Counter"
fdc=[FDC2..FDC0];
FD0..FD7 node istype 'reg'; "Fake Data"
fd=[FD7..FD0];
equations

"We assert Transmit Byte Load, TBL, elsewhere in the code"
"when we want to clock ram_data.pin into the Transmit Byte."
TBL.clk = DCK;
TBL.aclr = RESET; 

"The Transmit Byte, tb, holds a byte for transmission to"
"the LWDAQ driver."
tb.clk = DCK;
tb.aclr = RESET;

"The Transmitter State, ts, controls serial transmission"
"to the LWDAQ driver of the Transmi Byte."
ts.clk = DCK;
ts.aclr = RESET;
state_diagram ts;
  state ^d0:if DS & DTX then 1 else 0;
  state 1:
    if !DTX then 0;
    if DTX & TBL then 2;
    if DTX & !TBL then 1;
  state 2:goto 3;"Start Bit"
  state 3:goto 4;"Start Bit"
  state 4:goto 5;"TB7"
  state 5:goto 6;"TB7"
  state 6:goto 7;
  state 7:goto 8;
  state 8:goto 9;
  state 9:goto 10;
  state 10:goto 11;
  state 11:goto 12;
  state 12:goto 13;
  state 13:goto 14;
  state 14:goto 15;
  state 15:goto 16;
  state 16:goto 17;
  state 17:goto 18;
  state 18:goto 19;"TB0"
  state 19:goto 20;"TB0"
  state 20:goto 0;"Stop Bit"
equations;

"TBO is the output of the bit transmitter. It passes through"
"the LVDS return and so along the cables to the driver."
TBO = (
    (ts==0)  & 1   "Idle Bit 1"
  # (ts==1)  & 1   "Idle Bit 1"
  # (ts==2)  & 0   "Start Bit 0"
  # (ts==3)  & 0   "Start Bit 0"
  # (ts==4)  & TB7
  # (ts==5)  & TB7
  # (ts==6)  & TB6
  # (ts==7)  & TB6
  # (ts==8)  & TB5
  # (ts==9)  & TB5
  # (ts==10) & TB4
  # (ts==11) & TB4
  # (ts==12) & TB3
  # (ts==13) & TB3
  # (ts==14) & TB2
  # (ts==15) & TB2
  # (ts==16) & TB1
  # (ts==17) & TB1
  # (ts==18) & TB0
  # (ts==19) & TB0
  # (ts==20) & 1   "Stop Bit 1"
);

"We return TBO to the driver when DTX is set."
when DTX then B = TBO;

"We load the transmitter byte from the RAM data bus. When"
"some other part of the firmware asserts TBL."
when !fake_data then {
  tb.clk = DCK;
  tb.aclr = RESET;
  when TBL then tb:=ram_data.pin;
  else tb:=tb;
}

"We can generate fake data to check for errors in the"
"upload to the LWDAQ driver, as opposed to errors in"
"RF reception. The Recorder instrument will interpret"
"the fake data as a time stamp."
fdc.clk=DCK;
fdc.aclr=IRST;
fd.clk=DCK;
fd.aclr=IRST;
when fake_data then {
  TBL=1;
  when (ts==20) then fdc:=fdc+1;
  else fdc:=fdc;
  when (fdc==0) then tb:=1;
  when (fdc==1) then tb:=fd;
  when (fdc==2) then tb:=fd;
  when (fdc==3) then tb:=fd;
  when (fdc==4) then tb:=2;
  when (fdc==5) then tb:=fd;
  when (fdc==6) then tb:=fd;
  when (fdc==7) then tb:=fd;
  when (ts==20) & (fdc==7) then fd:=fd+1;
  else fd:=fd;
}


"Sample Session"
"--------------"

declarations
SSS1..SSS0 node istype 'reg'; "Sample Session State"
sss = [SSS1..SSS0];
ASS0..ASS5 node istype 'reg'; "ADC Sample Sate"
ass = [ASS5..ASS0];
ST0..ST15 node istype 'reg'; "Sample Timer"
st = [ST15..ST0];
STR node istype 'reg'; "Sample Timer Reset"
START node istype 'com,keep'; "Start Sample Session"
equations

"We need the START node to reduce the number"
"of logic inputs to the sss state machine."
START = IS & (operation == SSS);

sss.aclr = IRST;
sss.clk = DCK;
state_diagram sss;
  state ^d0: 
    if START then 1 else 0;
  state 1: 
    if (nsc == 0) then   "50"
      1;
    if (nsc == 1) then { "51"
      if (num_samples >= 64) then 2
      else 1
    }
    if (nsc == 2) then { "52"
      if (num_samples >= 512) then 2
      else 1
    }
    if (nsc == 3) then { "53"
      if (num_samples >= 5120) then 2
      else 1
    }
    if (nsc == 4) then { "54"
      if (num_samples >= 50176) then 2
      else 1
    }
    if (nsc >= 5) then   "55-5F"
      2;
  state 2: goto 3;
  state 3: goto 0;
equations

DAR.clk = DCK;
DAR := (sss == 3) # IRST;

ass.aclr = IRST;
ass.clk = DCK;
when (ass == 0) then {
  when (sss == 1) then ass:=1
  else ass:=0;
}
when (ass > 0) & (ass < 63) then {
  ass:=ass+1;
}
when (ass == 63) then {
    when (src == 0) then {  "40 0Hz"
      ass:=63;
    }
    when (src == 1)  then { "41 1kHz"
      when (st == 40000-2) then ass:=0
      else ass:=63
    }
    when (src == 2)  then { "42 2kHz"
      when (st == 20000-2) then ass:=0
      else ass:=63
    }
    when (src == 3)  then { "43 5kHz"
      when (st == 8000-2) then ass:=0
      else ass:=63
    }
    when (src == 4)  then { "44 10kHz"
      when (st == 4000-2) then ass:=0
      else ass:=63
    }
    when (src == 5)  then { "45 20kHz"
      when (st == 2000-2) then ass:=0
      else ass:=63
    }
    when (src == 6)  then { "46 50kHz"
      when (st == 800-2) then ass:=0
      else ass:=63
    }
    when (src == 7)  then { "47 100kHz"
      when (st == 400-2) then ass:=0
      else ass:=63
    }
    when (src == 8)  then { "48 200kHz"
      when (st == 200-2) then ass:=0
      else ass:=63
    }
    when (src == 9)  then { "49 500kHz"
      when (st == 80-2) then ass:=0
      else ass:=63
    }
    when (src >= 10) then { "4B-4F 1.25MHz"
      ass:=0;
    }
}

"We reset the sample timer whenever ass is zero."
"We use a dedicated node for the reset signal. By"
"resetting with the .aclr input instead of in logic,"
"we allow the chip to implement the sample timer"
"as a synchronous ripple counter made out of T-type"
"flip-flops, which greatly decreases the number of"
"logic terms the sample counter requires."
STR.clk = DCK;
STR := (ass == 0);
st.aclr = STR;
st.clk = DCK;
st:=st+1;

DAI.clk = DCK;
DAI := (ass > 54) & (ass < 63);

!SS1 = (ass >= 1) & (ass <= 36);
SCK1 = !ASS0 & (ass >= 1) & (ass <= 34);
SDI1 = 0;
SS2 = SS1;
SCK2 = SCK1;
SDI2 = 0;


"Indicators Lamps"
"----------------"

RECEIVE.clk = DCK;
RECEIVE := 0;
UPLOAD = DS;
EMPTY = 1;

"Test Points"
"-----------"

TP1 = (sss!=0);
TP2 = SS1;

end