"<pre>
module P2080A

title 'P2080A'

"Version 1"

"[15-DEC-16] Start with P2082A03 and change pin numbers. The LEDs may be operated"
"in one of four modes, as set by DC2..DC1. When the mode is zero, the LEDs are all"
"off. When mode is one, a single LED is set to full power as selected by DC16..DC9."
"When mode is two, a single LED is set to three-quarter power as selected by the"
"bits DC16..DC9. When mode is three, all LEDs are turned on to ten percent power."

"Version 2"

"[03-FEB-17] Add new graduations of intensity and eliminate the all-LED command for"
"now."

declarations

"Constants"
da_delay = 7; "CK periods to DA"
dda_delay = 16; "CK periods to DDA"
run_time = dda_delay+3; "CK periods to run"

"Inputs"
A pin 64; "LVDS Input"

"Outputs"
B pin 69 istype 'com'; "LVDS Output"
LB pin 72 istype 'com'; "Loop Back"			
WAKE pin 48 istype 'com'; "Wake"
TP1..TP3 pin 59, 60, 54 istype 'com';
S1..S36 pin 58, 55, 53, 61, 16, 17, 19, 15, 21, 22,
  28, 20, 30, 31, 34, 29, 41, 44, 47, 36, 
  66, 87, 84, 81, 91, 100, 97, 94, 11, 8, 
  9, 10, 6, 3, 4, 5 istype 'com';

"Command Receiver Nodes"
SA node istype 'reg'; "Synchronized A"
DSA node istype 'reg'; "Delayed SA"
DA node istype 'reg'; "Delayed A Rising Edge"
DDA node istype 'reg'; "Delayed DA"
AA node istype 'reg'; "Address Active"
CA node istype 'reg'; "Command Active"
ER,Q1..Q16 node istype 'reg'; "Receiver Bits"
LT4..LT0 node istype 'reg'; "LWDAQ Timer"
lt = [LT4..LT0];
DS node istype 'com'; "Data Strobe"
DC1..DC16 node istype 'reg';"Device Command Bits"
DA0..DA15 node istype 'reg';"Device Address Bits"

"Ring Oscillator Notes"
RO1,RO2 node istype 'com,keep'; "Ring Oscillator"
CK node istype 'reg,keep'; "Clock"
RUN node istype 'reg,keep';
equations 


"Clock Generation"
"----------------"

"The RUN flag controls the ring oscillator. When the ring"
"oscillator runs, it causes lt to increment. When lt reaches"
"a threshold, we clear the RUN flag."
RUN.aclr = (lt == run_time);
RUN := 1;
RUN.clk = A;

"Here we generate our clock with a ring oscillator."
"The ring oscillator consists of two combinatorial gates."
RO1 = RO2;
RO2 = !RO1 & RUN;
CK.clk = RO1;
CK:=!CK;


"Command and Address Decoding"
"----------------------------"

"This LWDAQ receiver uses the 40-MHz data clock to generate"
"the DA and DDA signals. We synchronise the incoming serial"
"logic signal, A, with the data clock."


"We synchronize A with DCK, and provide a delayed"
"version of A that allows us to detect edges."
[SA,DSA].clk = CK;
SA := A;
DSA := SA;

"This timer allows us to generate the Delayed A (DA)"
"and Double-Delayed A (DDA) signals for serial reception."
lt.clk = CK;
lt.aclr = !RUN;
lt := lt+1;
DA.clk = !CK;
DA := (lt==da_delay);
DDA.clk = !CK;
DDA := (lt==dda_delay);

"The command or address bits enter a sixteen-bit shift register."
[ER,Q1..Q16].clk = DA;
[ER,Q1..Q16] := [SA,ER,Q1..Q15];

"Address Active, or AA, provides a pulse that begins with DDA"
"on the start bit of an address transmission, and ends with DDA"
"on the stop bit of an address transmission. We clock the receiver"
"bits into the address register on a rising edge of AA."
AA.clk = DDA;
AA := (!AA & !CA & !SA & !ER) # (AA & !SA);
[DA0..DA15].clk = !AA;
[DA0..DA15] := [Q1..Q16];

"Command Active, or CA, provides a pulse that begins with DDA"
"on the start bit of a command transmission, and ends with DDA"
"on the stop bit of a command transmission. We clock the receiver"
"bits into the command register on a rising edge of CA."
CA.clk = DDA;
CA := (!AA & !CA & !SA & ER) # (CA & !SA);
[DC1..DC16].clk = !CA;
[DC1..DC16] := [Q1..Q16];

"Data Strobe identifies a solitary low pulse on A. A"
"solitary low pulse, combined with DTX, indicates that"
"the drivers is expecting this device to upload eight"
"bits of data."
DS = DDA & SA & !AA & !CA;


"Command Bit Allocation"
"----------------------"


"WAKE bit."
WAKE = DC8;

"We enable the return LVDS driver when DC7 is set."
LB = DC7;

"When the loopback bit is set, we send B back to A. When we"
"implement a data device, we will allow B to take on values"
"generated by a data transmitter state machine. For now, we"
"just set B = A always."
when LB then {
  B = A
} else {
  B = A
}




"Switching Signal Clock"
"----------------------"

"We need a 150-kHz switching signal with 7% duty cycle for our"
"A2080A buck converter. We start with a ring oscillator and then"
"divide down to 150 kHz. We use the divider count to set the duty"
"cycle. We enable the ring oscillator whenever DC1 is set. With"
"DC2 clear, the pulse is the length required for full power. With"
"DC2 set, the pulse is the length required for the LED to glow"
"visibly."

declarations
SR0..SR2 node istype 'com,keep'; "Switching Ring"
SD0..SD10 node istype 'reg'; "Switching Divider"
sd = [SD10..SD0];
end_0 = 0;
end_1 = 5;
end_2 = 10;
end_3 = 15;
end_4 = 20;
end_5 = 35;
end_6 = 30;
end_7 = 45;
period_end = 540;
SCK node istype 'reg'; "Switching Clock"
mode = [DC3..DC1];
equations

SR2 = SR1 & (mode != 0);
SR1 = SR0;
SR0 = !SR2;

sd.aclr = CA;
sd.clk = SR2;
when (sd == period_end) then {
  sd := 0;
} else {
  sd := sd + 1;
}

SCK.clk = SR2;
SCK.aclr = CA;
SCK := (sd < end_1) & (mode == 1)
  # (sd < end_2) & (mode == 2)
  # (sd < end_3) & (mode == 3)
  # (sd < end_4) & (mode == 4)
  # (sd < end_5) & (mode == 5)
  # (sd < end_6) & (mode == 6)
  # (sd < end_7) & (mode == 7);


"Switching Signals"
"-----------------"

"We select one of the LEDs using the top eight bits of the command word, except"
"we use only DC9..DC14, the lowest five bits of these eight, to obtain a number"
"between 0 and 63."

declarations
select = [DC14..DC9];
equations

S1 = (select == 1) & SCK;
S2 = (select == 2) & SCK;
S3 = (select == 3) & SCK;
S4 = (select == 4) & SCK;
S5 = (select == 5) & SCK;
S6 = (select == 6) & SCK;
S7 = (select == 7) & SCK;
S8 = (select == 8) & SCK;
S9 = (select == 9) & SCK;
S10 = (select == 10) & SCK;
S11 = (select == 11) & SCK;
S12 = (select == 12) & SCK;
S13 = (select == 13) & SCK;
S14 = (select == 14) & SCK;
S15 = (select == 15) & SCK;
S16 = (select == 16) & SCK;
S17 = (select == 17) & SCK;
S18 = (select == 18) & SCK;
S19 = (select == 19) & SCK;
S20 = (select == 20) & SCK;
S21 = (select == 21) & SCK;
S22 = (select == 22) & SCK;
S23 = (select == 23) & SCK;
S24 = (select == 24) & SCK;
S25 = (select == 25) & SCK;
S26 = (select == 26) & SCK;
S27 = (select == 27) & SCK;
S28 = (select == 28) & SCK;
S29 = (select == 29) & SCK;
S30 = (select == 30) & SCK;
S31 = (select == 31) & SCK;
S32 = (select == 32) & SCK;
S33 = (select == 33) & SCK;
S34 = (select == 34) & SCK;
S35 = (select == 35) & SCK;
S36 = (select == 36) & SCK;

"Test Points"
"-----------"

TP1 = sd == 0;
TP2 = SCK;
TP3 = CA;

end