"<pre>
module P2065B

title 'P2065B'

"Version 2, Last Modified 11-May-06."

"Here we use a ring oscillator to generate a 40-MHz"
"clock for the LWDAQ data receiver. We add gates to"
"the ring oscillator until the period of the clock"
"we observe on the FCKO pin is as close to 25 ns"
"as we can get it."

"The code below contains a full LWDAQ command, address"
"and data strobe receiver. Most of the nodes declared"
"for the receiver will be eliminated by the compiler,"
"because the A2065B does not use them."

"Pins"
declarations
A pin 70; "LVDS input"
B pin 59 istype 'com'; "LVDS output"
LB pin 60 istype 'com'; "Loop Back"
!RESET pin 72;"RESET"			
ARCK pin 93; "Asynchronous 32 kHz clock input"
DCK pin 39 istype 'com';"Delayed A Clock on Global CLK2"
DCKO pin 42 istype 'com'; "Source of DA"
SQR pin 50 istype 'com'; "Square Wave"
DXP pin 6 istype 'com'; "Drive X+"
SXP pin 4 istype 'com'; "Select X+"
DXM pin 3 istype 'com'; "Drive X-"
SXM pin 5 istype 'com'; "Select X-"
DYP pin 17 istype 'com'; "Drive Y+"
SYP pin 16 istype 'com'; "Select Y+"
DYM pin 8 istype 'com'; "Drive Y-"
SYM pin 19 istype 'com'; "Select Y-"
SCTR pin 20 istype 'com'; "Select Center"
SSIN pin 22 istype 'com'; "Select SIN"
SCOM pin 28 istype 'com'; "Select VCOM"
SGND pin 21 istype 'com'; "Select Ground"
equations 


"Data Clock Generation"
"---------------------"

"Here we generate the data clock using a ring oscillator."
"Buffer the ring oscillator output with DCKO to isolate"
"the ring from its loads."
declarations
R1..R10 node istype 'com,keep'; "Ring Oscillator"
equations

"Each gate in the ring oscillator adds two propagation delays"
"to the data clock period. With the LC4256V-10I we find that"
"eight gates gives us a period of 24.4 ns. Each gate contributes"
"roughly 3 ns. With a chip this fast or faster, the largest"
"deviation from 25 ns we will have to accept is 1.5 ns. Our main"
"concern for accuracy in the data clock is serial byte upload"
"to the LWDAQ driver. This upload requires that ten clock cycles"
"take 250+-20 ns. Our ring oscillator can be calibrated to 250"
"+-15 ns."
[R10..R1]=[R9..R1,!R10 & !RESET];
DCKO=R1;


"Reference Clock"
"---------------"

"The reference clock is exactly 30.768 kHz, and we use it for"
"our longer time measurements."

declarations
RCK node istype 'reg,keep'; "Reference Clock"
equations

RCK.clk = DCK;
RCK := ARCK;


"LWDAQ Command and Address Decoding"
"----------------------------------"

"This LWDAQ receiver uses the 40-MHz data clock to generate"
"the DA and DDA signals. We synchronise the incoming serial"
"logic signal, A, with the data clock."

declarations
SA node istype 'reg'; "Synchronized A"
DSA node istype 'reg'; "Delayed SA"
DA node istype 'com,keep'; "Delayed A Rising Edge"
DDA node istype 'com,keep'; "Delayed DA"
AA node istype 'reg'; "Address Active"
DAA node istype 'reg'; "Delayed AA"
CA node istype 'reg'; "Command Active"
DCA node istype 'reg'; "Delayed CA"
ER,Q1..Q16 node istype 'reg'; "Receiver Bits"
LT3..LT0 node istype 'reg'; "LWDAQ Timer"
lt = [LT3..LT0];
AS node istype 'reg'; "Address Strobe"
CS node istype 'reg'; "Command Strobe"
DS node istype 'reg'; "Data Strobe"
DC1..DC16 node istype 'reg';"Device Command Bits"
DA0..DA15 node istype 'reg';"Device Address Bits"
WAKE node istype 'com'; "Wake"
DTX node istype 'com'; "Device Transmit"
equations

"We synchronize A with DCK, and provide a delayed"
"version of A that allows us to detect edges."
[SA,DSA].clk = DCK;
[SA,DSA].aclr = RESET;
SA := A;
DSA := SA;

"This timer allows us to generate the Delayed A (DA)"
"and Double-Delayed A (DDA) signals for serial reception."
lt.clk = DCK;
lt.aclr = RESET;
when lt==0 then {
  when SA & !DSA then lt:=1
  else lt:=0;
} else {
  when lt==9 then lt:=0
  else lt:=lt+1;
}
DA = (lt==4);
DDA = (lt==9);

"We use DCK to clock the receiver registers, and RESET to"
"clear them."
[ER,Q1..Q16,AA,DAA,AS,CA,DCA,CS,DS,DC1..DC16,DA0..DA15].clk = DCK;
[ER,Q1..Q16,AA,DAA,AS,CA,DCA,CS,DS,DC1..DC16,DA0..DA15].aclr = RESET;

"We move bits along the shift register on DA."
when DA then [ER,Q1..Q16] := [SA,ER,Q1..Q15];
else [ER,Q1..Q16] := [ER,Q1..Q16];

"Address Active provides a pulse that begins with DDA"
"on the start bit of an address transmission, and ends"
"with the stop bit of an address transmission. Delayed"
"AA allows us to create Address Strobe, or AS. Address"
"Strobe provides a pulse at the end of an address"
"reception. We clock the receiver bits into the address"
"register on a rusing edge of AS."
when DDA then AA := (!AA & !CA & !SA & !ER) # (AA & !SA)
else AA := AA;
DAA := AA;
AS := DAA & !AA;
when AS then [DA0..DA15] := [Q1..Q16]
else [DA0..DA15] := [DA0..DA15];

"Command Active provides a pulse that begins with DDA"
"on the start bit of a command transmission, and ends"
"with the stop bit of a command transmission. Delayed"
"CA allows us to create Command Strobe, or CS. Command"
"strobe provides a pulse at the end of each command"
"reception. We clock the receiver bits into the command"
"register on a rusing edge of CS."
when DDA then CA := (!AA & !CA & !SA & ER) # (CA & !SA)
else CA := CA;
DCA := CA;
CS := DCA & !CA;
when CS then [DC1..DC16] := [Q1..Q16]
else [DC1..DC16] := [DC1..DC16];

"Data Strobe identifies a solitary low pulse on A. A"
"solitary low pulse, combined with DTX, indicates that"
"the drivers is expecting this device to upload eight"
"bits of data."
DS := DDA & SA & !AA & !CA;


"Command Bit Allocation"
"----------------------"

"WAKE bit."
WAKE = DC8;

"We enable the return LVDS driver when DC7 is set."
LB = DC7;

"We loop back A to the driver."
B = A;

"We use the first three device command bits (DC3..DC1) to"
"select which signal will be returned to the driver. We have"
"to make sure that [DC3..DC1] == 0 corresponds to the return"
"of VCOM, or else the LWDAQ loop-back won't work."
declarations
  channel_select=[DC3..DC1];
equations

SCOM = (channel_select == 0);
SGND = (channel_select == 1);
SSIN = (channel_select == 2);
SCTR = (channel_select == 3);
SXP  = (channel_select == 4);
SXM  = (channel_select == 5);
SYP  = (channel_select == 6);
SYM  = (channel_select == 7);

"When DC4 and DC5 are zero, we drive all four outer pins of the"
"sensor. By driving the sensor, we make sure all the coupling"
"capacitors are charged correctly before we begin acquisition."
"If we don't pre-charge the coupling capacitors, the sin waves"
"will be offset for the first few measurements as the capacitors"
"charge up. This offset can be large enough to drive the sin"
"waves out of the range of the driver's ADC."
DXP  =  !DC4;
DXM  =  !DC4;
DYP  =  !DC5;
DYM  =  !DC5;


"Square Wave Generator"
"---------------------"

declarations
CD4..CD0 node istype 'reg'; "Clock Divider"
div=[CD4..CD0]; "CK divider"
equations

div.aclr=RESET;
div.clk=RCK;
when div==0 then div:=27
else div:=div-1;
SQR = (div<14); "test point on board"

end