module P2060B

title 'P2060B'

"(C) Kevan Hashemi 2014"

"Version 1: [22-OCT-14] A template program with LWDAQ command and address"
"receiver, and a data transmitter as well, to send bytes back to the driver"
"The data transmitter will respond with a byte that increments each time"
"we read it with the read_job applied to a data_type device. We reset the"
"byte with command bit one (DC1). We flash the indicator lights also,"
"to make sure they work, and we can reverse the flash movement by setting"
"command bit two (DC2)."

declarations

"Fixed Pins"
A pin 12;"LVDS input"
B pin 64 istype 'com';"LVDS output"
!RESET pin 37;"RESET"           
CK pin 38;"40 MHz clock input"
WAKE pin 66 istype 'com';"WAKE"
LB pin 65 istype 'com';"Loop Back, enables LVDS driver"
TP1..TP4 pin 69,70,71,72 istype 'com,keep';"
LED16..LED1 pin 41..44,47..50,53..56,58..61 istype 'reg,keep';

"IO Pins"
"IO1..IO10 pin 3,4,5,6,8,9,10,11,14,15 istype 'com';
IO1..IO3 pin 3,4,5 istype 'com';
IO4, IO5, IO6 pin 6, 8, 9;

"Nodes"               
SA node istype 'reg,keep';"Synchornized A."
DA node istype 'com,keep';"Delayed SA"
DDA node istype 'com,keep';"Delayed Delayed SA"
ACTIVE node istype 'reg,keep';"transmission active"
D1..D9 node istype 'reg,keep';"delay pipeline."
DRS0..DRS2 node istype 'reg,keep';"Command Receiver State"
CS node istype 'com,keep';"Command Strobe"
NCS node istype 'com,keep';"New Command Strobe"
AS node istype 'com,keep';"Address Strobe"
NAS node istype 'com,keep';"New Address Strobe"
DS node istype 'com,keep';"Data Strobe"
ER,Q1..Q16 node istype 'reg';"Receiver Bits"
DA0..DA15 node istype 'reg';"Device Address Bits"
DC1..DC16 node istype 'reg';"Device Command Bits"
DTX node istype 'com'; "Data Transmit"

"Sets"
drs=[DRS2..DRS0];"Command Receiver State"

equations


"Serial Input Decoding"
"---------------------"

"We synchronize the incoming LVDS logic signal to"
"our 40-MHz clock."
SA:=A;
SA.clk=CK;

"We put SA through a pipeline of registers clocked"
"with CK so that we can generate the delayed timing"
"pulses from the rising edge of SA."
[D1..D9]:= [SA,D1..D8];
[D1..D9].clk= CK;
[D1..D9].aclr=RESET;

"Delayed SA provides is asserted for one CK period 125 ns"
"after any rising edge of SA. We use DA and SA to obtain"
"the LWDAQ data bit. If SA is high with DA, the data bit"
"is one."
DA = D4 & !D5;

"Delayed Delayed SA is asserted for one CK period 250 ns"
"after any rising edge of SA. We use DDA and SA to obtain"
"the LWDAQ ACTIVE bit. If SA is low with DDA, ACTIVE is"
"true."
DDA = D8 & !D9;

"We assert ACTIVE whenever the driver is transmitting"
"a command data bit."
ACTIVE.clk=CK;
ACTIVE.aclr=RESET;
when !SA & DDA then ACTIVE:=1;
when SA & DDA then ACTIVE:=0;
when !DDA then ACTIVE:=ACTIVE;

"We clock the receiver shift register and the entry"
"register with CK, and we clear them on RESET."
[ER,Q1..Q16].clk=CK;
[ER,Q1..Q16].aclr=RESET;

"We shift the receiver bits whenever we have DA"
"asserted. We clock the current value of SA into"
"the entry register (ER), and shift all the other"
"bits over by one. At the beginning of a LWDAQ"
"transmission, ER contains a 1 if the transmission"
"is a command, and 0 if it is an address. At the"
"end of a transmission, ER contains a 1, and Q1"
"to Q16 contain the transmitted sixteen-bit word,"
"either address or command."
when DA then [ER,Q1..Q16]:=[SA,ER,Q1..Q15];
else [ER,Q1..Q16]:=[ER,Q1..Q16].fb;


"Data Receiver"
"-------------"

"Data Receiver states."
declarations

rest=0;
command_receive=1;
clock_command_register=2;
address_receive=3;
clock_address_register=4;
new_command_strobe=5;
new_address_strobe=6;

equations

drs.clk=CK;
drs.aclr=RESET;

state_diagram drs;
  "Stay in the rest state until we receive ACTIVE."
  "When ACTIVE, we proceed with command receive"
  "if the data bit in ER is one, otherwise an address"
  "receive."
  state rest:
    if ACTIVE then {
      if ER then command_receive
      else address_receive;
   } else rest;

  "We stay in command_receive until !ACTIVE."
  state command_receive:
    if !ACTIVE then clock_command_register
    else command_receive;

  "As we pass through clock_command_register we"
  "indicate that it is time to clock the receiver"
  "bits into the command register."
  state clock_command_register:goto new_command_strobe;

  "As we pass through new_command_strobe we start"
  "any action that should be taken when the new command"
  "arrives. The variable NCS is true when drs is in"
  "the new_command_strobe state."
  state new_command_strobe:goto rest;

  "We stay in address_receive until !ACTIVE."
  state address_receive:
    if !ACTIVE then clock_address_register;
    else address_receive ;

  "As we pass through clock_address_register we"
  "indicate that it is time to clock the receiver"
  "bits into the address register."    
  state clock_address_register:goto new_address_strobe;   

  "As we pass through new_address_strobe we start"
  "any action that should be taken when the new address"
  "arrives. The variable NAS is true when drs is in"
  "the new_address_strobe state."
  state new_address_strobe:goto rest;
equations


"Command Strobe is asserted for one CK period at the"
"end of a command transmission from the LWDAQ driver."
CS = (drs==clock_command_register);

"New Command Strobe follows CS when the new command"
"is already established in the DC registers."
NCS = (drs==new_command_strobe);

"Address Strobe is asserted for one CK period at the"
"end of an address transmission from the LWDAQ driver."
AS = (drs==clock_address_register);

"New Address Strobe follows AS when the new address"
"is already established in the DA registers."
NAS = (drs==new_address_strobe);

"Data Strobe is asserted for one CK period after a"
"solitary low pulse from the LWDAQ driver. The driver"
"uses solitary low pulses that endure for 125 ns and"
"are followed by a > 375 ns high pulse to initiate"
"serial transmission of data from LWDAQ devices of type"
"data_device, like this one."
DS = (SA & DDA & (drs==rest));

"We clock the receiver bits into the command register"
"on CS."
[DC1..DC16].clk=CK;
[DC1..DC16].aclr=RESET;
when CS then [DC1..DC16]:=[Q1..Q16]
else [DC1..DC16]:=[DC1..DC16];

"We clock the receiver bits into the address register"
"on AS."
[DA0..DA15].clk=CK;
[DA0..DA15].aclr=RESET;
when AS then [DA0..DA15]:=[Q1..Q16]
else [DA0..DA15]:=[DA0..DA15].fb;


"Commands"
"--------"

"Wake on DC8."
WAKE=DC8;

"Looback on DC7."
LB = DC7 # DTX;

"Data Transmit on DC5."
DTX = DC5;

"Loop back A to B for loopback job."
when !DTX then B = A;

"We use DC1 to clear the transmit byte (see below)"

"We use DC2 to reverse the LED flashing."


"Data Transmitter"
"----------------"

"The transmitter sends bytes back to the driver. It waits for"
"DS combined with DTX (DC5). When it receives DS and DTX, it"
"waits for Transmission Byte Load (TBL). The transmitter uses"
"DCK to time its serial transmission to the driver. It transmits"
"a leading zero followed by the eight bits of the transmission"
"byte (tb)."

declarations
TS4..TS0 node istype 'reg'; "Transmit State"
ts=[TS4..TS0];"Transmission State"
TBD7..TBD0 node istype 'reg'; "Transmission Bits"
tbd=[TBD7..TBD0]; "Transmission Byte Data"
TBO node istype 'com,keep'; "Transmitter Bit Out"
equations

"The Transmitter State, ts, controls serial transmission"
"to the LWDAQ driver of the Transmi Byte."
ts.clk = CK;
ts.aclr = RESET;
state_diagram ts;
  state 0:if DS & DTX then 1 else 0;
  state 1:goto 2;
  state 2:goto 3;"Start Bit"
  state 3:goto 4;"Start Bit"
  state 4:goto 5;"TBD7"
  state 5:goto 6;"TBD7"
  state 6:goto 7;
  state 7:goto 8;
  state 8:goto 9;
  state 9:goto 10;
  state 10:goto 11;
  state 11:goto 12;
  state 12:goto 13;
  state 13:goto 14;
  state 14:goto 15;
  state 15:goto 16;
  state 16:goto 17;
  state 17:goto 18;
  state 18:goto 19;"TBD0"
  state 19:goto 20;"TBD0"
  state 20:goto 0;"Stop Bit"
equations;

"TBO is the output of the bit transmitter. It passes through"
"the LVDS return and so along the cables to the driver."
TBO = (
    (ts==0)  & 1   "Idle Bit 1"
  # (ts==1)  & 1   "Idle Bit 1"
  # (ts==2)  & 0   
  # (ts==3)  & 0
  # (ts==4)  & TBD7
  # (ts==5)  & TBD7
  # (ts==6)  & TBD6
  # (ts==7)  & TBD6
  # (ts==8)  & TBD5
  # (ts==9)  & TBD5
  # (ts==10) & TBD4
  # (ts==11) & TBD4
  # (ts==12) & TBD3
  # (ts==13) & TBD3
  # (ts==14) & TBD2
  # (ts==15) & TBD2
  # (ts==16) & TBD1
  # (ts==17) & TBD1
  # (ts==18) & TBD0
  # (ts==19) & TBD0
  # (ts==20) & 1   "Stop Bit 1"
);

"We return TBO to the driver when DTX is set."
when DTX then B = TBO;

"We increment the transmit byte after we read it, and reset"
"it with DC16."
tbd.aclr = DC1;
tbd.clk = CK;
when (ts==20) then {tbd := tbd + 1} else {tbd := tbd};


"Microsecond Clock"
"------------------"

declarations
MUT0..MUT5 node istype 'reg,keep';
muts = [MUT5..MUT0];
MUCK node istype 'reg,keep';
us_per_MUCK = 40;
equations

muts.aclr = RESET;
muts.clk = CK;
when muts == us_per_MUCK - 1 then {
  muts := 0;
} else {
  muts := muts + 1;
}
MUCK.clk = CK;
when muts < us_per_MUCK / 2 then MUCK := 0
else MUCK := 1;


"Millisecond Clock"
"-----------------"

declarations
MMT0..MMT9 node istype 'reg,keep';
mmts = [MMT9..MMT0];
MMCK node istype 'reg,keep';
us_per_MMCK = 1000;
equations

mmts.aclr = RESET;
mmts.clk = MUCK;
when mmts == us_per_MMCK - 1 then {
  mmts := 0;
} else {
  mmts := mmts + 1;
}
MMCK.clk = CK;
when mmts < us_per_MMCK / 2 then MMCK := 0
else MMCK := 1;


"4 Hz Clock"
"------------"

declarations
MST0..MST9 node istype 'reg,keep';
msts = [MST9..MST0];
MSCK node istype 'reg,keep';
us_per_MSCK = 250;
equations

msts.aclr = RESET;
msts.clk = MMCK;
when msts == us_per_MSCK - 1 then {
  msts := 0;
} else {
  msts := msts + 1;
}
MSCK.clk = CK;
when msts < us_per_MSCK / 2 then MSCK := 0
else MSCK := 1;


"Outputs"
"-------"

[LED2..LED16].aclr = RESET;
LED1.ap = RESET;
[LED1..LED16].clk = MSCK;
when !DC2 then [LED1..LED16] := [LED16,LED1..LED15];
else [LED1..LED16] := [LED2..LED16,LED1];

[TP1..TP4] = [DC1..DC4];

end